The present invention generally relates to an information processing system or apparatus such as an electronic computer or the like. More particularly, the invention is concerned with an information processing system or apparatus and a neural computer such as an analogue computer, neural network and the like which are capable of performing information processings with a high degree of parallel operation.
A so-called analogue computer includes a plurality of functional blocks such as address, integrators and others, wherein each of the functional blocks receives signals outputted from the other functional block or blocks directly or by way of a scaler circuit having a multiplication function, a sign inverter and others. The functional block then performs arithmetic operations such as addition, integration and others on the signal as received to thereby determine its own output value which is then transmitted to the other functional block or blocks. Usually, it is determined by an operator in accordance with problems as imposed which of the functional block's output is to be inputted to which of the functional blocks and what numerical value is to be set in the scaler circuit.
In the network known as a neural net or network, there are provided, as shown in FIG. 1 of the accompanying drawings, a plurality of cell bodies and functional circuits 10 referred to as dendrites, wherein each of the functional circuits receives signals outputted from the other functional circuit through the medium of a scaler 11. Each of the functional blocks each composed of the functional circuit 10 and the scaler circuit 11 arithmetically determines a total sum of the values represented by the signals as its own internal value and outputs a signal corresponding to the internal value to the other functional blocks. Selection of the coefficients (hereinafter referred to as the weight values) for the individual scalers are automatically determined through a process usually referred to as the learning. An example of this type neural network is disclosed in a Japanese periodical "NIKKEI ELECTRONICS", No. 427 (Aug. 10, 1987), pp. 115-124.
An attempt for implementing the neural network in the form of a semiconductor integrated circuit is disclosed in a Japanese periodical "NIKKEI MICRODEVICE", July 1988, pp. 44-89. One of such semiconductor integrated circuits for the neural network is also discussed in "A CMOS ASSOCIATIVE MEMORY CHIP BASED ON NEURAL NETWORKS": 1987 ISSCC DIGEST OF TECHNICAL PAPERS, pp. 304-305. In "NIKKEI MICRODEVICE", July, 1988, pp. 72 to 78, there is proposed a neural network by using digital circuits. The digital circuits are easy to be integrated and can ensure a high accuracy for operations by virtue of high insusceptibility to noise and manufacturing tolerance. Disadvantageous however is the digital circuit in that a greater number of parts or elements are required when compared with the analogue circuit Under the circumstance, in the case of the abovementioned approach, the numerical values which are usually expressed by pulse codes are expressed in terms of pulse numbers for simplification of the circuit configuration.